Constant bandwidth DC offset correction in an amplifier

ABSTRACT

According to one embodiment, a system for constant bandwidth DC offset correction in an amplifier includes a number of amplifier stages having an input and an output coupled together in series. The system for constant bandwidth DC offset correction further includes a number of DC offset correction feedback loops which include a variable gain transconductor coupled to an integration capacitor further coupled to a fixed gain transconductor. Each of the DC offset correction feedback loops are coupled to the input and output of each of the number of amplifier stages. The transconductance of the variable gain transconductor in each of the number of DC correction feedback loops is varied in relation to a gain of the number of amplifier stages, such that the DC offset correction feedback loops provide DC offset correction while maintaining a constant bandwidth.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is generally in the field of circuits. Morespecifically, the invention is in the field of amplifier circuits.

2. Background Art

Direct conversion receiver architectures are desirable in radio designsbecause they are able to down-convert an incoming Radio Frequency (“RF”)signal to an Intermediate Frequency (“IF”) signal, thereby eliminatingthe need for external RF/IF filter blocks and consequently reducing thecost of the receiver. However, direct conversion receivers typicallysuffer from random DC offset voltages which may be caused by localoscillator self mixing and DC offsets present in the active amplifierstages. These random DC offset voltages can undesirably saturate theactive amplifier stages.

In order to reduce the DC offset voltages, a feedback loop is typicallyused around the active amplifier stage to suppress the DC offsetvoltages. A conventional feedback loop operates by monitoring the outputof the amplifier stage and by providing a correction voltage at theinput of the amplifier stage. However, to avoid cancellation of anydesired input signals, the feedback loop must be band-limited. Since thebandwidth of the feedback loop changes with the gain of the amplifierstage, the gain of the amplifier stage must remain fixed for thebandwidth of the feedback loop to remain constant. As such, inapplications where the gain of the amplifier stage is continuouslyvaried by an analog control signal, the conventional feedback loopcannot maintain a constant bandwidth to provide proper DC offsetcorrection.

Accordingly, there is a need in the art for a system and method for DCoffset correction of an amplifier using feedback loops which maintain aconstant bandwidth as the gain of the amplifier is continuously varied.

SUMMARY OF THE INVENTION

The present invention is directed to a system and method for constantbandwidth DC offset correction in an amplifier. The present inventionaddresses and resolves the need in the art for a system and method forDC offset correction of an amplifier using feedback loops which maintaina constant bandwidth as the gain of the amplifier is continuouslyvaried.

According to an exemplary embodiment, a system for constant bandwidth DCoffset correction of an amplifier includes a number of amplifier stagescoupled in series, where each of the amplifier stages includes an inputand an output. For example, each two adjacent amplifier stages can becoupled together in series through a unity gain buffer amplifier.According to this embodiment, the input and output of each amplifierstage can include differential inputs and outputs. For example, eachamplifier stage can include an automatic gain control (“AGC”) amplifierand can be an intermediate frequency (“IF”) amplifier in a directconversion receiver (“DCR”).

The system for constant bandwidth DC offset correction further includesa number of DC offset correction feedback loops. Each of the DC offsetcorrection feedback loops include a variable gain transconductor coupledto an integration capacitor further coupled to a fixed gaintransconductor, where each of the DC offset correction feedback loopsare coupled to the input and output of each of the amplifier stages.

According to this embodiment, the system for constant bandwidth DCoffset correction can further include a control circuit having an inputand first and second outputs, where the control circuit is configured toreceive a gain control signal at the input and provide a first controlsignal at the first output which controls the gain of the amplifierstages and a second control signal at the second output which controlsthe transconductance of the variable gain transconductor in each DCoffset correction feedback loop. For example, the gain control signalcan be an analog voltage signal and the first control signal and thesecond control signal can both be exponential signals which areinversely related.

According to this embodiment, the transconductance of the variable gaintransconductor in each of the number of DC correction feedback loops isvaried in relation to a gain of the number of amplifier stages, suchthat the number of DC offset correction feedback loops provide DC offsetcorrection while maintaining a constant bandwidth. For example, thevariable gain transconductor is required to provide a minimumtransconductance of 500 nanosiemens (nS). Other features and advantagesof the present invention will become more readily apparent to those ofordinary skill in the art after reviewing the following detaileddescription and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of an amplifier circuit havingcontinuous DC offset correction at a constant bandwidth in accordancewith one embodiment of the present invention.

FIG. 2 illustrates a circuit diagram of a variable gain transconductor.

FIG. 3 illustrates a circuit diagram of a transconductor.

FIG. 4 illustrates exemplary first and second control output signals inaccordance with one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to a system and method for constantbandwidth DC offset correction in an amplifier. The followingdescription contains specific information pertaining to theimplementation of the present invention. One skilled in the art willrecognize that the present invention may be implemented in a mannerdifferent from that specifically discussed in the present application.Moreover, some of the specific details of the invention are notdiscussed in order not to obscure the invention. The specific detailsnot described in the present application are within the knowledge of aperson of ordinary skill in the art.

The drawings in the present application and their accompanying detaileddescription are directed to merely exemplary embodiments of theinvention. To maintain brevity, other embodiments of the invention whichuse the principles of the present invention are not specificallydescribed in the present application and are not specificallyillustrated by the present drawings. It should be noted that similarnumerals generally refer to similar elements in the various drawings.

FIG. 1 shows a block diagram of an amplifier circuit having continuousDC offset correction at a constant bandwidth in accordance with oneembodiment of the present invention. Amplifier circuit 100 can be, forexample, an intermediate frequency (“IF”) amplifier circuit used in adirect conversion receiver (“DCR”). As shown in FIG. 1, amplifiercircuit 100 includes amplifier stages 102 a and 102 b, buffer amplifier130, and control circuit 132.

As shown in FIG. 1, amplifier stages 102 a and 102 b each includerespective automatic gain control (“AGC”) amplifiers 104 a and 104 b, DCoffset correction loops 120 a and 120 b, and input resistors (“Rin”) 110a and 110 b. As also shown in FIG. 1, DC offset correction loops 120 aand 120 b each include respective variable gain transconductors 124 aand 124 b, transconductors 122 a and 122 b, and integration capacitors126 a and 126 b. As shown in FIG. 1, amplifier stage 102 a is coupled inseries with amplifier stage 102 b through buffer amplifier 130. Bufferamplifier 130 can be, for example, a unity gain buffer which can be usedto provide isolation between amplifier stages 102 a and 102 b. Althoughthe embodiment of the invention shown in FIG. 1 includes only twoamplifier stages (i.e., amplifier stages 102 a and 102 b), it isunderstood that the invention can be applied to amplifier circuitshaving additional amplifier stages.

As shown in FIG. 1, amplifier stage 102 a can receive input signals viadifferential inputs 106 and 108. Differential inputs 106 and 108 arecoupled to the differential inputs of AGC amplifier 104 a at nodes 112 aand 114 a, respectively. AGC amplifier 104 a can be, for example, anintermediate frequency automatic gain control (IF AGC) amplifier havingdifferential inputs and outputs. The differential outputs of AGCamplifier 104 a are coupled to the differential inputs of bufferamplifier 130 at nodes 116 a and 118 a and the differential outputs ofbuffer amplifier 130 are coupled to the differential inputs of AGCamplifier 104 b at nodes 112 b and 114 b. As shown in FIG. 1, thedifferential outputs of AGC amplifier 104 b are coupled to differentialoutputs 140 and 142 at nodes 116 b and 118 b, respectively.

As also shown in FIG. 1, the differential outputs of AGC amplifiers 104a and 104 b are coupled to respective variable gain transconductors 124a and 124 b in respective DC offset correction feedback loops 120 a and120 b. The differential outputs of variable gain transconductors 124 aand 124 b are respectively coupled to the differential inputs oftransconductors 122 a and 122 b. As shown in FIG. 1, the first andsecond terminals of integration capacitor 126 a are respectively coupledto nodes 128 a and 129 a, and the first and second terminals ofintegration capacitor 126 b are respectively coupled to nodes 128 b and129 b. The differential outputs of transconductor 122 a are coupled tothe differential inputs of AGC amplifier 104 a at nodes 112 a and 114 a,respectively, and the differential outputs of transconductor 122 b arecoupled to the differential inputs of AGC amplifier 104 b at nodes 112 band 114 b, respectively.

As shown in FIG. 1, amplifier circuit 100 includes control circuit 132which includes AGC signal input 134. Control circuit 132 furtherincludes a first output which is coupled to variable gaintransconductors 124 a and 124 b at node 138 and a second output which iscoupled to AGC amplifiers 104 a and 104 b at node 136.

The gain of each amplifier stage in amplifier circuit 100 is controlledby an AGC signal, which can be an analog voltage, provided to AGC signalinput 134 of control circuit 132. As such, in amplifier circuit 100, thegain of each amplifier stage, e.g., amplifier stages 102 a and 102 b,can be varied continuously by varying the AGC signal. For example, asshown in FIG. 1, control circuit 132 provides a first output signal,such as an AGC control current (“I_(AGC)”) 135 to AGC amplifiers 104 aand 104 b and a second output signal, such as transconductance controlcurrent (“I_(gm)”) 133 to variable gain transconductors 124 a and 124 b.As discussed below, the second output signal controls thetransconductance of variable gain transconductors 124 a and 124 b inrespective DC offset correction feedback loops 120 a and 120 b.

The operation of DC offset correction feedback loops 120 a and 120 bwill now be discussed with reference to DC offset correction feedbackloop 120 a to maintain brevity. DC offset correction feedback loop 120 ain FIG. 1 provides DC offset correction to amplifier stage 102 a byreceiving the differential output signals of AGC amplifier 104 a atnodes 116 a and 118 a and by providing an appropriate current throughresistor 110 a. Thus, a voltage equal in magnitude and opposite inpolarity to a DC offset voltage present at the differential inputs ofAGC amplifier 104 a is generated across resistor 110 a and across thedifferential inputs of AGC amplifier 104 a, which corrects the DC offsetvoltage existing at the differential inputs of AGC amplifier 104 a.

During operation of amplifier circuit 100, the differential outputsignals of AGC amplifier 104 a are continuously received by DC offsetcorrection feedback loop 120 a at the differential inputs of variablegain transconductor 124 a. Variable gain transconductor 124 a (andvariable gain transconductor 124 b) in FIG. 1 can be represented byvariable gain transconductor circuit 224 shown in FIG. 2. As shown inFIG. 2, variable gain transconductor circuit 224 includes voltage tocurrent converter 250 which includes positive differential input(“Vin+”) 256, negative differential input (“Vin−”) 258, transistors 252and 254, and variable gain transconductor resistor (“R_(gm1)”) 259.Variable gain transconductor circuit 224 further includes analogmultiplier 260 which includes transistors 262, 264, 266, and 268, commonmode voltage input (“Vcm”) 278, positive differential output current(“I_(out+)”) 280, negative differential output current (“I_(out−)”) 282,transistors 274 and 276, and transconductance control current source(“I_(gm)”) 233. In exemplary variable gain transconductor circuit 224,transistors 252, 254, 274, and 276 are PFETs and transistors 262, 264,266, and 268 are NPN bipolar transistors. Variable gain transconductorcircuit 224 further includes reference current sources 270 and 272, eachreference current source 270 and 272 providing approximately one-half ofa reference current (“I_(ref)”).

As shown in exemplary variable gain transconductor circuit 224 in FIG.2, the differential output signals of AGC amplifier 102 a in FIG. 1 areprovided to positive differential input (“Vin+”) 256 and negativedifferential input (“Vin−”) 258 of voltage to current converter 250. Invariable gain transconductor circuit 224, voltage to current converter250 drives analog multiplier 260, which has a linear controlcharacteristic. The gain of analog multiplier 260 can be modified byvarying transconductance control current (“I_(gm)”) 233. As shown inFIG. 1, I_(gm) 133 which corresponds to I_(gm) 233 in FIG. 2 iscontrolled by the first output of control circuit 132. Therefore, thetransconductance (G_(m1)) of variable gain transconductor circuit 224can be represented by equation 1:

G _(m1)=(I _(gm))/(I _(ref) *R _(gm1))  (equation 1)

where I_(gm) is the transconductance control current, I_(ref) is thebias current for variable gain transconductor circuit 224, and R_(gm1)is the resistance of variable gain transconductor resistor (“R_(gm1)”)259. Thus, as shown in FIG. 2, variable gain transconductor circuit 224provides differential output currents at positive differential currentoutput 280 and negative differential current output 282 in response toDC offset voltages sensed between positive differential input (Vin+) 256and negative differential input (Vin−) 258 of voltage to currentconverter 250.

In amplifier circuit 100, the differential output currents generated byvariable gain transconductor 124 a flow through integration capacitor126 a to generate a voltage across integration capacitor 126 a. Thevoltage across capacitor 126 a is then provided to the differentialinputs of transconductor 122 a, which can be, for example, a fixed gaintransconductor such as transconductor circuit 322 shown in FIG. 3.

Transconductor circuit 322 in FIG. 3 includes transistors 384 and 386,transconductor resistor (“R_(gm2)”) 394, transconductor resistor(“R_(gm3)”) 396, bias current sources (“I_(bias)”) 398 and 399, positivedifferential current output 382, negative differential current output380, positive differential voltage input 390, and negative differentialvoltage input 388. As discussed above, the voltage across integrationcapacitor 126 a is provided to the differential inputs, i.e., positivedifferential voltage input 390 and negative differential voltage input388, of transconductor circuit 322. Transconductor circuit 322,therefore, coverts the voltage across capacitor 126 a to a pair ofdifferential output currents, such as I_(out+) and I_(out−), at positivedifferential current output 380 and negative differential current output382, respectively. For example, transconductor circuit 322 can provide again of −20 db to attenuate any noise generated from variable gaintransconductor 124 a in FIG. 1.

Transconductor circuit 322 also provides a common mode control signal(“Vcm”) at Vcm output 392, which is provided to Vcm input 278 ofvariable gain transconductor circuit 224 in FIG. 2, in order to reducethe common mode voltage at positive differential current output 280 andnegative differential current output 282. As shown in FIG. 1, thedifferential output currents generated by transconductor 122 a flowthrough resistor 110 a and produce a voltage across resistor 110 a andacross the differential inputs of AGC amplifier 104 a. The voltageacross resistor 110 a is equal in magnitude but opposite in polarity toa DC offset voltage present across the differential inputs of AGCamplifier 104 a, thereby reducing the DC offset voltage. DC offsetcorrection feedback loop 120 a, therefore, provides negative feedbackfrom the differential outputs of AGC amplifier 104 a to the differentialinputs of AGC amplifier 104 a in amplification stage 102 a.

By way of background, when a feedback loop is used to monitor thedifferential outputs of an AGC amplifier and to provide negativefeedback to the differential inputs of the AGC amplifier to correct a DCoffset voltage, desired input signals at the differential inputs of theAGC amplifier may be undesirably canceled. However, such cancellation ofdesired input signals may be avoided if the negative feedback loop isband-limited such that the desired bandwidth of the feedback loopremains constant as the gain of the AGC amplifier varies. For example,the response of feedback loop 120 a can be represented by the transferfunction shown in equation 2:

H(s)=(A _(AGC) *G _(m1) *G _(m2) *R _(in) *H(f))/(s*C)  (equation 2)

where A_(AGC) is the gain of AGC amplifier 120 a, G_(m1) is thetransconductance of variable gain transconductor 124 a, G_(m2) is thetransconductance of transconductor 122 a, R_(in) is the resistance ofresistor 110 a, H(f) is the frequency response of filters used in AGCamplifier 120 a (not shown in FIG. 1), and C is the capacitance ofintegration capacitor 126 a. Since the terms G_(m2), R_(in), H(f), and Cin equation 2 are constant, DC offset correction feedback loop 120 a canmaintain a constant bandwidth over different values of A_(AGC) if theproduct of the A_(AGC) and G_(m1) terms remains constant.

As shown in FIG. 1, the first output signal of control circuit 132,i.e., I_(AGC) 135, controls the gain of each AGC amplifier (e.g., AGCamplifiers 104 a and 104 b) in amplifier circuit 100 and the second gaincontrol output signal, i.e., I_(gm) 133, controls the transconductanceof each variable gain transconductor (e.g., variable gaintransconductors 124 a and 124 b) in respective DC offset correctionfeedback loops 120 a and 120 b. Exemplary first and second controloutput signals provided by control circuit 132 are shown in FIG. 4. FIG.4 shows transconductance control current (“I_(gm)”) 433 which can be thefirst output signal provided by control circuit 132 and automatic gaincontrol current (“I_(AGC)”) 435 which can be the second output signal.The value of the AGC signal (“V_(AGC)”) that is provided to AGC signalinput 134 of control circuit 132 is represented by the x-axis in volts(“V”). The first y-axis (which intersects the x-axis at 0.5V) representsthe value of I_(gm) 133 in microamperes (uA) and the second y-axis(which intersects the x-axis at 1.5V) represents the value of I_(AGC)135 in microamperes (uA).

As shown in FIG. 4, as V_(AGC) increases, I_(AGC) increasesexponentially while I_(gm) decreases exponentially, and as I_(AGC)decreases exponentially, I_(gm) increases exponentially. Thus, asI_(AGC) is increased, the gain (i.e., the A_(AGC) term in equation 2) ofAGC amplifier 104 a is also increased. As I_(gm) is decreased, thetransconductance (i.e., the G_(m1) term in equation 2) of variable gaintransconductor 124 a is also decreased. This configuration allows the DCoffset correction feedback loop of AGC amplifier 120 a to provide theappropriate negative feedback voltage to the differential inputs of AGCamplifier 120 a, based on the gain of AGC amplifier 120 a. As shown inFIG. 4, the product of I_(gm) and I_(AGC) for any value of V_(AGC) is aconstant. Therefore, since I_(gm) controls the transconductance (i.e.,the G_(m1) term in equation 2) of variable gain transconductor 124 a andsince the gain (i.e., the A_(AGC) term in equation 2) is controlled byI_(AGC), the product of the G_(m1) and A_(AGC) terms is also a constant.Thus, the response of DC offset correction feedback loop 120 arepresented by equation 2 above is advantageously band-limited, therebyallowing DC offset correction feedback loop 120 a to provide continuousDC offset correction at a constant bandwidth even as the gain of AGCamplifier 104 a is continuously varied.

Thus, since amplifier circuit 100 includes two amplifier stages, i.e.,amplifier stages 102 a and 102 b, amplifier circuit 100 can provide again of 80 db by configuring each of amplifier stages 102 a and 102 b toprovide a gain of 40 db. Since the gain of each amplifier stage 102 aand 102 b is substantially less than the total gain of amplifier circuit100 (e.g., a gain of 80 db), the minimum required transconductance ofeach variable gain transconductor 124 a and 124 b for proper operationof respective DC offset correction feedback loops 120 a and 120 b isadvantageously increased, for example, to approximately 500 nanosiemens(nS). As such, the invention allows the size of integration capacitors126 a and 126 b to be advantageously decreased to provide stable andreliable integration.

From the above description of the invention it is manifest that varioustechniques can be used for implementing the concepts of the presentinvention without departing from its scope. Moreover, while theinvention has been described with specific reference to certainembodiments, a person of ordinary skill in the art would appreciate thatchanges can be made in form and detail without departing from the spiritand the scope of the invention. Thus, the described embodiments are tobe considered in all respects as illustrative and not restrictive. Itshould also be understood that the invention is not limited to theparticular embodiments described herein but is capable of manyrearrangements, modifications, and substitutions without departing fromthe scope of the invention.

Thus, system and method for constant bandwidth DC offset correction inan amplifier have been described.

1-20. (canceled)
 21. A system for constant bandwidth DC offsetcorrection in an amplifier, said system comprising: a plurality ofamplifier stages coupled in series, each of said plurality of amplifierstages having an input and an output; a plurality of DC offsetcorrection feedback loops, wherein each of said plurality of DC offsetcorrection feedback loops is coupled to a respective one of saidplurality of amplifier stages; wherein said plurality of DC offsetcorrection feedback loops provide DC offset correction while maintaininga constant bandwidth.
 22. The system of claim 21, further comprising acontrol circuit having an input and a first output, said control circuitreceiving a gain control signal at said input and providing a firstcontrol signal at said first output to control a gain of said pluralityof amplifier stages.
 23. The system of claim 21 wherein each twoadjacent amplifier stages in said plurality of amplifier stages arecoupled together in series through a buffer amplifier.
 24. The system ofclaim 23 wherein said buffer amplifier is a unity gain buffer amplifier.25. The system of claim 21, wherein said input and output of each ofsaid plurality of amplifier stages comprise differential inputs andoutputs.
 26. The system of claim 22, wherein said gain control signal isan analog voltage.
 27. The system of claim 21, wherein each of saidplurality of amplifier stages comprises an automatic gain control (AGC)amplifier.
 28. The system of claim 27, wherein said automatic gaincontrol amplifier is an intermediate frequency (“IF”) amplifier in adirect conversion receiver (“DCR”).
 29. A method for constant bandwidthDC offset correction in an amplifier, said amplifier comprising aplurality of amplifier stages coupled in series, each of said pluralityof amplifier stages having an input and an output, wherein a pluralityof DC offset correction feedback loops are coupled to said input andsaid output of each of said plurality of amplifier stages, said methodcomprising: sensing a DC offset voltage at said output of each of saidplurality of amplifier stages; correcting said DC offset voltage so asto maintain an approximately constant bandwidth.
 30. The method of claim29, wherein said correcting said DC offset voltage causes said pluralityof DC offset correction feedback loops and said amplifier to maintainsaid approximately constant bandwidth.
 31. The method of claim 29,wherein said correcting said DC offset voltage comprises providing avoltage approximately equal in magnitude and opposite in polarity tosaid DC offset voltage.
 32. The method of claim 30, wherein saidcorrecting said DC offset voltage comprises providing a voltageapproximately equal in magnitude and opposite in polarity to said DCoffset voltage.
 33. The method of claim 29, wherein said amplifiercomprises a control circuit having an input and a first output, saidcontrol circuit receiving a gain control signal at said input andproviding a first control signal at said first output to control a gainof said plurality of amplifier stages.
 34. The method of claim 29,wherein each two adjacent amplifier stages in said plurality ofamplifier stages are coupled together in series through a bufferamplifier.
 35. The method of claim 34, wherein said buffer amplifier isa unity gain buffer amplifier.
 36. The method of claim 29, wherein saidinput and output of each of said plurality of amplifier stages comprisedifferential inputs and outputs.
 37. The method of claim 33, whereinsaid gain control signal is an analog voltage.
 38. The method of claim29, wherein each of said plurality of amplifier stages comprises anautomatic gain control (AGC) amplifier.
 39. The method of claim 38,wherein said automatic gain control amplifier is an intermediatefrequency (“IF”) amplifier in a direct conversion receiver (“DCR”).